Unix Systems For Modern Architectures -1994- Pdf -

Old UNIX ran all device interrupts on the single CPU. On SMP, interrupt routing is critical. Modern architectures (PCI-based Intel MP spec 1.1, SGI's IRIX, Sun's SBus) support interrupt vectors that can be directed to any CPU.

The traditional UNIX buffer cache—a pool of memory pages used to cache disk blocks—is obsolete on modern architectures for two reasons. First, the virtual memory system can now page directly from the filesystem (using mmap() and clustered pageins). Second, on SMP systems, the buffer cache lock becomes a global bottleneck.

The next three years will determine whether UNIX becomes the universal OS for tera-scale computing or fragments into proprietary SMP variants (Windows NT is breathing down our necks). As of April 1994, the smart money is on UNIX—but only if the Berkeley and System V traditions can merge into a truly scalable, modern kernel. unix systems for modern architectures -1994- pdf

By 1994, the 4GB virtual address space of 32-bit UNIX is a cage. Database servers (Oracle 7, Informix OnLine) want to map 64GB of shared memory for buffer pools. The Alpha AXP (OSF/1), UltraSPARC (Solaris 2.4 preview), and MIPS R8000 (IRIX 6) all offer full 64-bit kernels.

Consider the traditional sleep() / wakeup() mechanism. In a single-CPU UNIX, this was elegant. In an SMP, it requires a "rendezvous" interrupt to all CPUs, flushing TLBs and invalidating cache lines. A 1994 benchmark on an SGI Challenge (12x MIPS R4400) showed that a simple select() loop on 1000 file descriptors caused 40% of kernel time to be spent in cross-CPU TLB shootdowns. Old UNIX ran all device interrupts on the single CPU

Senior Systems Analyst, UNIX Research Group Date: April 17, 1994

The original UNIX kernel—a masterpiece of simplicity—assumed a single CPU, a single memory bus, and an I/O subsystem that was slow compared to the CPU. Today, that kernel becomes the bottleneck. The "Big Kernel Lock" (BKL) found in many commercial UNIXes (System V Release 4, early BSD derivatives) is no longer viable. When a 150MHz Alpha processor sits idle waiting for a spinlock held by a 50MHz SuperSPARC, the system's scalability collapses. The traditional UNIX buffer cache—a pool of memory

UNIX for Modern Architectures: Scalability, SMP, and the Post-RISC Era (1994)